DIVSEL=DIV1, SRC=XOSC0
Generic Clock Generator Control
| SRC | Source Select 0 (XOSC0): XOSC0 oscillator output 1 (XOSC1): XOSC1 oscillator output 2 (GCLKIN): Generator input pad 3 (GCLKGEN1): Generic clock generator 1 output 4 (OSCULP32K): OSCULP32K oscillator output 5 (XOSC32K): XOSC32K oscillator output 6 (DFLL): DFLL output 7 (DPLL0): DPLL0 output 8 (DPLL1): DPLL1 output |
| GENEN | Generic Clock Generator Enable |
| IDC | Improve Duty Cycle |
| OOV | Output Off Value |
| OE | Output Enable |
| DIVSEL | Divide Selection 0 (DIV1): Divide input directly by divider factor 1 (DIV2): Divide input by 2^(divider factor+ 1) |
| RUNSTDBY | Run in Standby |
| DIV | Division Factor |